1. Field of the Invention
Example embodiments relate to an E-beam lithography system and, more particularly, to an E-beam lithography system that may synchronously irradiate surfaces of a plurality of photomasks.
2. Description of the Related Art
As semiconductor technology continues to develop, advancements in semiconductor devices, especially memory devices, are improving. That is, high speed, low power consumption, high capacity, miniaturized memory devices are being developed. As semiconductor memory devices are improved, technologies for improving integration are becoming even more important.
Improving the integration of semiconductor devices is being achieved through the development of new and/or improved circuit design techniques, materials, and various process techniques. Patterning techniques are important in improving the integration of semiconductor devices. Through the patterning technique, the pattern of unit devices, such as transistors, for example, may be finely formed on a wafer.
Patterning techniques generally include a photolithography technique and an etching technique. The photolithography technique may include fabricating a photomask and transferring a pattern to a wafer using the photomask. A photomask fabricating technique refers to a technique for forming a pattern to be transferred to a wafer on a photomask. If a pattern is formed on the photomask, the pattern should be formed to have the correct shape and a uniform size. Further, the substrate and the pattern should not have defects. The substrate may be a glass substrate, for example. Another important consideration is that an ideal layer-to-layer overlay alignment tolerance of the photomasks should be zero.
If a semiconductor chip is produced on a wafer, various patterns and unit devices may be formed using several photomasks. As a result, a finished semiconductor chip may operate correctly only if the patterns formed on the wafer using the several photomasks are precisely aligned. If even one layer is placed incorrectly and/or is misaligned, a finished unit device may not function properly, which may cause the finished semiconductor including the unit device to be inoperable and/or malfunction. Therefore, it is important for photomasks used in fabricating a semiconductor chip to have precise layer-to-layer overlay alignment.
Further, in the case of a fine pattern, duplicate exposure may be performed on a wafer using a plurality of photomasks to form one layer of a pattern, thereby further increasing the importance of layer-to-layer overlay alignment of photomasks.
In order to align the patterns formed on the photomasks, factors including registration and orthogonality may be used.
Registration refers to an alignment factor indicating how precisely the pitch, size, and interval of the patterns in the X and/or Y direction match ideal and/or computer data.
Orthogonality refers to the angles of the X and/or Y directions of the patterns. Various patterns may have several shapes created by combining lines in the X-direction and lines in the Y-direction and/or patterns in the X-direction and patterns in the Y-direction. As such, orthogonality refers to a measure representing whether the lines in the X-direction are precisely perpendicular to the lines in the Y-direction and/or whether the patterns in the X-direction are precisely perpendicular to the patterns in the Y-direction.
Herein, registration and orthogonality are referred to generically as pattern alignment. If the photomasks are overlaid, the factor representing whether the pattern alignments match each other is referred to as layer-to-layer overlay alignment and is abbreviated herein as overlay alignment.
FIGS. 1A to 1D are views schematically illustrating pattern alignment and/or computer data of two photomasks, which may be fabricated using an E-beam lithography system. FIGS. 1A to 1D are used to further describe and illustrate examples of what is referred to herein as “pattern alignment” and a “difference in pattern alignment”. The drawings are somewhat exaggerated for ease of explanation. A photomask (a) and a photomask (b) may be photomasks that are separately fabricated and have the same pattern. Alternatively, the photomasks may be photomasks which are fabricated to be overlaid. Each of the photomasks may be individually fabricated.
FIG. 1A is an example view showing ideal pattern alignment, which may be computer data about patterns to be formed on photomasks.
The pattern of the photomask (a) and the pattern of the photomask (b) have an ideal pattern alignment in the X and Y directions meaning there is no error. Hence, if the two patterns shown in FIG. 1A are overlaid, the patterns of the photomask (a) and the pattern of the photomask (b) correspond. However, because the photomasks shown in FIG. 1A represent ideal pattern alignment, photomasks having the pattern alignment shown in FIG. 1A are seldom realizable.
FIG. 1B is a view comparing an example photomask (a) having ideal pattern alignment with an example photomask (b) having a difference in pattern alignment.
In FIG. 1B, the photomask (a) has ideal pattern alignment corresponding to computer data, and the photomask (b) has pattern alignment in which the registration and orthogonality are slightly different from the computer data Thus, the photomasks shown in FIG. 1B may not precisely overlay each other.
If a pattern is formed using the photomasks shown in FIG. 1B, the pattern formed by the photomask (a) would not be precisely overlaid on the pattern formed by the photomask (b) and thus, a unit device would likely not be correctly produced. Thus, a finished semiconductor device including the unit device may be inoperable. Even if the finished semiconductor device including the unit device operates, the finished semiconductor device would likely have low reliability and/or durability.
FIG. 1C is a view comparing pattern alignment of example photomasks having the same degree of difference.
In FIG. 1C, both the photomask (a) and the photomask (b) have the same pattern alignment. If the photomasks are overlaid, the patterns formed from the photomasks may precisely correspond to each other. Thus, a semiconductor device fabricated using the photomasks of FIG. 1C may operate correctly. However, it is nearly impossible to fabricate the photomasks such that the photomasks have the same degree of difference using conventional techniques.
FIG. 1D is a view illustrating two example photomasks having different degrees of difference in pattern alignment. FIG. 1D illustrates a typical example of two photomasks formed using conventional techniques.
The photomask (a) and the photomask (b) illustrated in FIG. 1D have different pattern alignment. If a semiconductor device is fabricated using the photomasks, the pattern of an upper layer is not precisely overlaid on the pattern of a lower layer. As a result finished unit devices formed using the photomask (a) and the photomask (b) shown in FIG. 1D and a semiconductor device including the unit devices may malfunction and/or be inoperable.
For example, assuming that the photomask (a) is a line pattern and the photomask (b) is a via hole pattern, lines and via holes would likely not overlay each other if the example photomasks illustrated in FIGS. 1B and 1D were used and thus, an electric connection would likely not be created. Thus, the formed unit devices may be inoperable. If an electric connection is somewhat achieved using the example photomasks illustrated in FIGS. 1B and 1D, the lines and the via holes are likely only partially overlaid and thus, an electric resistance of the unit devices formed using the example photomasks illustrated in FIGS. 1B and 1D would likely be undesirably large. In this case, the unit devices may not operate smoothly. Accordingly, the reliability and the durability of a finished semiconductor device including these unit devices would decrease.
Further, if the example photomasks illustrated in FIG. 1D are overlaid on the example photomasks having ideal pattern alignment illustrated in FIG. 1A, a normal device may be formed. However, in this case, if the example photomasks have different pattern alignment, overlay alignment tolerance may increase. For example, the overlay alignment tolerance may be twice as much as that of the pattern alignment.
Thus, reducing and/or minimizing the overlay alignment tolerance of photomasks is generally more important than reducing and/or minimizing the pattern alignment tolerance photomasks.
Pattern alignment tolerance and overlay alignment tolerance may result from the motion error of a stage of conventional photomask fabricating equipment, which may move photomasks forwards, backwards, left, and right.
A conventional E-beam lithography system for fabricating photomasks may be operated such that an irradiating system radiating an electron beam irradiates a desired and/or predetermined position; and a stage on which photomasks is mounted moves forwards, backwards, left, and right, thus radiating the electron beam on the surfaces of the photomasks to form patterns. Conventionally, the precision of the mechanical movement of the stage determines the pattern alignment and the overlay alignment.
Using conventional devices and/or techniques, it is difficult to reduce and/or solve pattern misalignment issues, which refer to the overlay alignment tolerance of photomasks or overlaid photomasks.
The pattern alignment tolerance and the overlay alignment tolerance generally do not depend on the size of a pattern to be formed, but instead have a predetermined mechanical limit. Therefore, assuming that the pattern alignment tolerance for the design rule of a pattern is the tolerance rate of the photomask, the smaller the pattern to be formed, the larger the relative tolerance of the pattern alignment and/or the overlay alignment.
As described above, the relative tolerance of the pattern alignment and/or the overlay alignment affects the manufacturing process and circuit design, so that a circuit must be designed in consideration of the pattern alignment tolerance and/or the overlay alignment tolerance. When considering the pattern alignment tolerance and/or the overlay alignment tolerance, the size of each pattern is set to be larger than an ideal size, so that the margin for the process is relatively large. This is a major factor impeding the tendency toward the miniaturization of semiconductor devices.